Characterisation And Modeling Of Mismatch In MOS Transistors For Precision Analog Design

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Authors: Kadaba R LakshmikumarRobert A HadawayMiles A Copeland
Published in: IEEE Journal Of Solid-state Circuits
Year: 1986   
DOI: 10.1109/JSSC.1986.1052648
Citations: 263
EI: NO
Abstract:
a characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data the physical causes of mismatch are discussed in detail for both p and n channel devices statistical methods are used to develop analytical models that relate the mismatch to the device dimensions it is shown that these models are valid for small geometry devices only extensive experimental data from a 3 \? m cmos process are used to verify the models the application of the transistor matching studies to the design of a high performance digital to analog converter \( dac \) is discussed a circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices it has been possible to achieve a circuit yield of greater than 97 as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach
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