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Norman P Jouppi
HIndex: 28
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Efficient energy use
Dissipation
Cycle time variation
Register file
Dynamic priority scheduling
Dynamic random-access memory
Computer graphics
Reduced instruction set computing
Application software
Chip
32-bit
Semiconductor memory
Processor register
Computer architecture
Bandwidth
Computer network
CMOS
Multi-core processor
Process design
Computer hardware
Pipeline transport
Network switch
Performance
Integrated circuit
Very-large-scale integration
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Efficient energy use
Dissipation
Cycle time variation
Register file
Dynamic priority scheduling
Dynamic random-access memory
Computer graphics
Reduced instruction set computing
Application software
Chip
32-bit
Semiconductor memory
Processor register
Computer architecture
Bandwidth
Computer network
CMOS
Multi-core processor
Process design
Computer hardware
Pipeline transport
Network switch
Performance
Integrated circuit
Very-large-scale integration
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Match this author profile with one of the following researchers:
Author Name
Affiliation
Papers
Norman P Jouppi
University Of California San Diego
126
Norman P Jouppi
Stanford University
108
Norman P Jouppi
Hp Labs
18
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