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A J Van De Goor
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Stress
System testing
Mathematical model
Interference
Functional testing
Fault model
Chip
Computer hardware
Algorithm design
Shift register
Integrated circuit
Dram
Static random-access memory
Software Testing
Computer architecture
Design for testing
Fault detection and isolation
Semiconductor memory
Robustness
Information technology
Fault coverage
Logic gate
Decoding methods
Automatic test pattern generation
Logic
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Stress
System testing
Mathematical model
Interference
Functional testing
Fault model
Chip
Computer hardware
Algorithm design
Shift register
Integrated circuit
Dram
Static random-access memory
Software Testing
Computer architecture
Design for testing
Fault detection and isolation
Semiconductor memory
Robustness
Information technology
Fault coverage
Logic gate
Decoding methods
Automatic test pattern generation
Logic
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A J Van De Goor
Delft University Of Technology
106
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